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LTM4613 1 4613f pgood run comp intv cc drv cc f set track/ss fcb marg0 marg1 mpgm v out v fb v in 0.1f 10f 3 22pf c out v out 12v 8a c in v in 24v to 36v pllin clock sync LTM4613 sgnd v d pgnd margin control 51k 5.23k 392k 5% margin 4613 ta01 typical application features applications description en55022b compliant 36v in , 15v out , 8a, dc/dc module regulator the ltm ? 4613 is a complete, ultralow noise, 8a switch mode dc/dc power supply. included in the package are the switching controller, power fets, inductor and all support components. operating over an input voltage range of 5v to 36v, the LTM4613 supports an output voltage range of 3.3v to 15v, set by a single external resistor. only bulk input and output capacitors are needed to finish the design. high switching frequency and an adaptive on-time current mode architecture enables a very fast transient response to line and load changes without sacrificing stability. the onboard input filter and noise cancellation circuits achieve low noise coupling, thus effectively reducing the electromagnetic interference (emi)see figure 7. furthermore, the dc/dc module ? regulator can be syn - chronized with an external clock to reduce undesirable frequency harmonics and allow polyphase ? operation for high load currents. the LTM4613 is offered in a space saving and thermally enhanced 15mm 15mm 4.32mm lga package, which enables utilization of unused space on the bottom of pc boards for high density point-of-load regulation. the LTM4613 is pb-free and rohs compliant. 12v/8a ultralow noise module with 24v to 36v input n complete low emi switch mode power supply n en55022 class b compliant n wide input voltage range: 5v to 36v n 8a output current n 3.3v to 15v output voltage range n low input and output referred noise n output voltage tracking and margining n pll frequency synchronization n 2% maximum total dc error n power good tracks with margining n current foldback protection n parallel/current sharing n ultrafast transient response n current mode control n programmable soft-start n output overvoltage protection n C55c to 125c operating temperature range (LTM4613mpv) n small surface mount footprint, low profile (15mm 15mm 4.32mm) lga package n telecom and networking equipment n industrial and avionic equipment n rf systems radiated emission scan with 24v in to 12v out at 8a l , lt, ltc, ltm, module, polyphase, linear technology, and the linear logo are registered trademarks and ltpowercad is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. 70 60 50 40 30 signal amplitude (db uv/m) 20 10 0 30 226.2 422.4 613.6 frequency (mhz) 4613 ta01b 814.3 1010.0 ?10 en55022b limit
LTM4613 2 4613f pin configuration absolute maximum ratings intv cc, drv cc ............................................. C0.3v to 6v v out ........................................................... C0.3v to 16v pllin, fcb, track/ss, mpgm, marg0, marg1, pgood .................... C0.3v to intv cc + 0.3v run ............................................................. C 0.3v to 5v v fb , comp ................................................ C0.3v to 2.7v v in , v d ....................................................... C0.3v to 36v internal operating temperature range (note 2) e- and i-grades .................................. C40c to 125c mp-grade .......................................... C55c to 125c storage temperature range .................. C55c to 125c peak package body temperature .......................... 245c (note 1) marg1 drv cc v fb pgood sgnd nc nc nc fcb v in bank 1 v d pgnd bank 2 v out bank 3 f set marg0 run comp mpgm pllin intv cc v d track/ss lga package 133-lead (15mm 15mm 4.32mm) top view sgnd 12 21 43 5 6 98 10 11 7 a b c d e f g h j k l m t jmax = 125c, jctop = 17c/w, jcbottom = 2.3c/w, ja = 11c/w to 14c/w, ja derived from 95mm 76mm pcb with 4 layers weight = 1.7g order information lead free finish tray part marking* package description temperature range LTM4613ev#pbf LTM4613ev#pbf LTM4613v 133-lead (15mm 15mm 4.32mm) lga C40c to 125c LTM4613iv#pbf LTM4613iv#pbf LTM4613v 133-lead (15mm 15mm 4.32mm) lga C40c to 125c LTM4613mpv#pbf LTM4613mpv#pbf LTM4613v 133-lead (15mm 15mm 4.32mm) lga C55c to 125c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ this product is only offered in trays. for more information go to: http://www.linear.com/packaging/
LTM4613 3 4613f electrical characteristics the l denotes the specifications which apply over the full internal operating temperature range, otherwise specifications are at t a = 25c (note 2), v in = 24v, unless otherwise noted. per typical application (front page) configuration. symbol parameter conditions min typ max units v in(dc) input dc voltage l 5 36 v v out(dc) output voltage, total variation with line and load c in = 10f 3, c out = 47f 4; fcb = 0, v in = 24v to 36v, v out = 12v l 11.83 12.07 12.31 v input specifications v in(uvlo) undervoltage lockout threshold i out = 0a 3.2 4.8 v i inrush(vin) input inrush current at start-up i out = 0a; c in = 10f 3, c out = 47f 4; c ss = 22nf v out = 12v v in = 24v v in = 36v 150 120 ma ma i q(vin) input supply bias current v in = 36v, v out = 12v, switching continuous, i out = 0a v in = 24v, v out = 12v, switching continuous, i out = 0a shutdown, run = 0, v in = 36v 78 60 50 ma ma a i s(vin) input supply current v in = 36v, v out = 12v, i out = 8a v in = 24v, v out = 12v, i out = 8a 2.90 4.26 a a v intvcc internal v cc voltage v in = 36v, run > 2v, i out = 0a 4.7 5 5.3 v output specifications i out(dc) output continuous current range v in = 24v, v out = 12v (note 4) 0 8 a ?v out(line) v out line regulation accuracy v out = 12v, fcb = 0v, v in = 24v to 36v, i out = 0a l 0.05 0.3 % ?v out(load) v out load regulation accuracy v out = 12v, fcb = 0v, i out = 0a to 8a (note 4) v in = 36v v in = 24v l l 0.5 0.5 0.75 0.75 % % v in(ac) input ripple voltage i out = 0a, c in = 1 10f x5r ceramic and 1 100f electrolytic, 3 10f x5r ceramic on v d pins v in = 24v, v out = 12v (note 5) 10 mv p-p v out(ac) output ripple voltage i out = 0a, c out = 1 10f, 4 47f x5r ceramic v in = 24v, v out = 12v 19 mv p-p f s output ripple voltage frequency v in = 24v, v out = 12v, i out = 0a 600 khz ?v out(start) turn-on overshoot c out = 47f 4, v out = 12v, i out = 0a, c ss = 22nf v in = 36v v in = 24v 20 20 mv mv t start turn-on time c out = 47f 4, v out = 12v, i out = 0a, c ss = open v in = 36v v in = 24v 0.3 0.3 ms ms ?v out(ls) peak deviation for dynamic load load: 0% to 50% to 0% of full load c out = 1 10f, 3 47f x5r ceramic, 1 47f poscap v in = 24v, v out = 12v 250 mv t settle settling time for dynamic load step load: 0% to 50% to 0% of full load c out = 1 10f, 3 47f x5r ceramic, 1 47f poscap v in = 24v, v out = 12v 100 s i out(pk) output current limit c out = 47f 4 v in = 36v, v out = 12v v in = 24v, v out = 12v 12 12 a a
LTM4613 4 4613f note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the LTM4613 is tested under pulsed load conditions such that t j t a . the LTM4613e is guaranteed to meet performance specifications over the 0c to 125c internal operating temperature range. specifications over the C40c to 125c internal operating temperature range are assured by design, characterization and correlation with statistical process controls. the LTM4613i is guaranteed to meet specifications over the C40c to 125c internal operating temperature range. the LTM4613mp symbol parameter conditions min typ max units control section v fb voltage at v fb pin i out = 0a, v out = 12v l 0.591 0.6 0.609 v v run run pin on/off threshold 1 1.5 1.9 v i ss / track soft-start charging current v ss / track = 0v C1 C1.5 C2 a v fcb forced continuous threshold 0.57 0.6 0.63 v i fcb forced continuous pin current v fcb = 0v C1 C2 a t on(min) minimum on-time (note 3) 50 100 ns t off(min) minimum off-time (note 3) 250 400 ns r pllin pllin input resistor 50 k i drvcc current into drv cc pin v out = 12v, i out = 0a, drv cc = 5v 22 30 ma r fbhi resistor between v out and v fb pins 99.5 100 100.5 k v mpgm margin reference voltage 1.18 v v marg0 , v marg1 marg0, marg1 voltage thresholds 1.4 v pgood ?v fbh pgood upper threshold v fb rising 7 10 13 % ?v fbl pgood lower threshold v fb falling C7 C10 C13 % ?v fb(hys) pgood hysteresis v fb returning 1.5 % v pgl pgood low voltage i pgood = 5ma 0.2 0.4 v electrical characteristics the l denotes the specifications which apply over the full internal operating temperature range, otherwise specifications are at t a = 25c (note 2), v in = 24v, unless otherwise noted. per typical application (front page) configuration. is guaranteed and tested over the full C55c to 125c internal operating temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. note 3: 100% tested at die level only. note 4: see the output current derating curves for different v in , v out and t a . note 5: guaranteed by design.
LTM4613 5 4613f typical performance characteristics efficiency vs load current with 3.3v out (fcb = 0) efficiency vs load current with 5v out (fcb = 0) efficiency vs load current with 12v out (fcb = 0) efficiency vs load current with 15v out (fcb = 0) transient response from 12v in to 3.3v out transient response from 12v in to 5v out transient response from 24v in to 12v out start-up with 24v in to 12v out at i out = 0a start-up with 24v in to 12v out at i out = 8a (refer to figure 18) load current (a) 0 efficiency (%) 80 90 8 4613 g01 70 60 2 4 6 1 3 5 7 100 75 85 65 95 5v in , 3.3v out 12v in , 3.3v out 24v in , 3.3v out 36v in , 3.3v out load current (a) 0 efficiency (%) 80 90 8 4613 g02 70 60 2 4 6 1 3 5 7 100 75 85 65 95 12v in , 5v out 24v in , 5v out 36v in , 5v out load current (a) 0 efficiency (%) 80 90 8 4613 g03 70 60 2 4 6 1 3 5 7 100 75 85 65 95 20v in , 12v out 24v in , 12v out 28v in , 12v out 36v in , 12v out load current (a) 0 efficiency (%) 80 90 8 4613 g04 70 60 2 4 6 1 3 5 7 100 75 85 65 95 24v in , 15v out 28v in , 15v out 32v in , 15v out 36v in , 15v out i out 5a/div v out 100mv/div ac 100s/div load step: 0a to 4a c out = 1 47f poscap 1 10f ceramic capacitor and 3 47f ceramic capacitors 4613 g05 i out 5a/div v out 100mv/div ac 100s/div load step: 0a to 4a c out = 1 47f poscap 1 10f ceramic capacitor and 3 47f ceramic capacitors 4613 g06 i out 5a/div v out 200mv/div ac 100s/div load step: 0a to 4a c out = 1 47f poscap 1 10f ceramic capacitor and 3 47f ceramic capacitors 4613 g07 i in 200ma/div v out 5v/div 10ms/div soft-start capacitor: 0.1f c in = 2 10f ceramic capacitors and 1 100f os-con capacitor 4613 g08 i in 1a/div v out 5v/div 10ms/div soft-start capacitor: 0.1f c in = 2 10f ceramic capacitors and 1 100f os-con capacitor 4613 g09
LTM4613 6 4613f typical performance characteristics start-up with 24v in to 12v out at i out = 8a, t a = C55c short-circuit with 24v in to 12v out at i out = 0a short-circuit with 24v in to 12v out at i out = 8a v in to v out step-down ratio input ripple output ripple v in 100mv/div ac 1s/div v in = 24v v out = 12v at 8a resistive load c in = 2 10f ceramic capacitors and 1 100f os-con capacitor 4613 g14 v out 10mv/div ac 1s/div v in = 24v v out = 12v at 8a resistive load c out = 1 47f poscap 1 10f ceramic capacitor and 3 47f ceramic capacitors 4613 g15 i out 2a/div v out 5v/div 20ms/div 4613 g10 soft-start capacitor: 0.1f c in = 2 10f ceramic capacitors and 1 100f os-con capacitor i in 500ma/div v out 5v/div 20s/div 4613 g11 c out = 1 47f poscap, 1 10f ceramic capacitors and 3 47f ceramic capacitors i in 2a/div v out 5v/div 20s/div 4613 g12 c out = 1 47f poscap, 1 10f ceramic capacitors and 3 47f ceramic capacitors output voltage (v) 3.3 0 input voltage (v) 6 12 18 24 36 5 7 9 11 4613 g13 13 15 30
LTM4613 7 4613f pin functions v in (bank 1): power input pins. apply input voltage be - tween these pins and pgnd pins. recommend placing input decoupling capacitance directly between v in pins and pgnd pins. pgnd (bank 2): power ground pins for both input and output returns. v out (bank 3): power output pins. apply output load between these pins and pgnd pins. recommend placing output decoupling capacitance directly between these pins and pgnd pins (see the LTM4613 pin configuration below). v d (pins c1 to c7, b6 to b7, a6): top fet drain pins. add more high frequency ceramic decoupling capacitors between v d and pgnd to handle the input rms current and reduce the input ripple further. drv cc (pins c10, e11, e12): these pins normally con- nect to intv cc for powering the internal mosfet drivers. they can be biased up to 6v from an external supply with about 50ma capability. this improves efficiency at the higher input voltages by reducing power dissipation in the module. see the applications information section. intv cc (pin a7): this pin is for additional decoupling of the 5v internal regulator. pllin (pin a8): external clock synchronization input to the phase detector. this pin is internally terminated to sgnd with a 50k resistor. apply a clock above 2v and below intv cc subject to minimum on-time and minimum off-time requirements. see the applications information section. fcb (pin m12): forced continuous input. connect this pin t o sgnd to force continuous synchronization operation at light load or to intv cc to enable discontinuous mode operation at light load. track /ss (pin a9): output voltage tracking and soft-start pin. when the module is configured as a master output, then a soft-start capacitor is placed on this pin to ground to control the master ramp rate. a soft-start capacitor can be used for soft-start turn-on as a standalone regulator. slave operation is performed by putting a resistor divider from the master output to the ground, and connecting the center point of the divider to this pin. see the applications information section. mpgm (pins a12, b11): programmable margining in- put. a resistor from these pins to ground sets a current that is equal to 1.18v/r. this current multiplied by 10k will equal a value in millivolts that is a percentage of the 0.6v reference voltage. leave floating if margining is not used. see the applications information section. to parallel LTM4613s, each requires an individual mpgm resistor. do not tie mpgm pins together. f set (pin b12): frequency set internally to 600khz at 12v output. an external resistor can be placed from this pin to ground to increase frequency or from this pin to v in to reduce frequency. see the applications information section for frequency adjustment. LTM4613 pin configuration (see package description for pin assignments) marg1 drv cc v fb pgood sgnd nc nc nc fcb v in bank 1 v d pgnd bank 2 v out bank 3 f set marg0 run comp mpgm pllin intv cc v d track/ss lga package 133-lead (15mm 15mm 4.32mm) top view sgnd 12 21 43 5 6 98 10 11 7 a b c d e f g h j k l m
LTM4613 8 4613f v fb (pin f12): the negative input of the error ampli - fier. internally, this pin is connected to v out with a 100k 0.5% precision resistor. different output voltages can be programmed with an additional resistor between the v fb and sgnd pins. see the applications information section. marg0 (pin c12): lsb logic input for the margining function. together with the marg1 pin, the marg0 pin will determine if a margin high, margin low, or no margin state is applied. the pin has an internal pull-down resistor of 50k. see the applications information section. marg1 (pins c11, d12): msb logic input for the margin - ing function. together with the marg0 pin, the marg1 pin will determine if a margin high, margin low, or no margin state is applied. the pins have an internal pull-down resistor of 50k. see the applications information section. sgnd (pins d9, h12): signal ground pins. these pins connect to pgnd at output capacitor point. comp (pins a11, d11): current control threshold and error amplifier compensation point. the current com - parator threshold increases with this control voltage. the voltage ranges from 0v to 2.4v with 0.7v corresponding to zero sense voltage (zero current). pgood (pin g12): output voltage power good indicator. open-drain logic output that is pulled to ground when the output voltage is not within 10% of the regulation point, after a 25s power bad mask timer expires. run (pins a10, b9): run control pins. a voltage above 1.9v will turn on the module, and below 1v will turn off the module. a programmable uvlo function can be ac- complished with a resistor from v in to this pin that has a 5.1v zener to ground. maximum pin voltage is 5v. mtp (pins j12, k12, l12): no connect pins. leave float - ing. used for mounting to pcb. pin functions
LTM4613 9 4613f block diagram decoupling requirements symbol parameter conditions min typ max units c in external input capacitor requirement (v in = 24v to 36v, v out = 12v) i out = 8a 30 100 f c out external output capacitor requirement (v in = 24v to 36v, v out = 12v) i out = 8a 100 220 f specifications are at t a = 25c. use figure 1 configuration. + internal comp sgnd comp pgood run > 1.9v = on < 1v = off max = 5v marg1 marg0 mpgm fcb pllin c ss intv cc drv cc track/ss v fb f set 50k 133k r fb 5.23k 50k 100k v out 5.1v zener power control m1 v in 24v to 36v v d v out 12v at 8a m2 50k 10f 1f c in + c out pgnd 4613 f01 10k 4.7f 2.2h input filter noise cancel- lation 10f 50v 3 figure 1. simplified block diagram
LTM4613 10 4613f operation power module description the LTM4613 is a standalone nonisolated switch mo de dc/dc power supply. it can deliver 8a of dc output cur - rent with minimal external input and output capacitors. this module provides a precisely regulated output voltage programmable via one external resistor from 3.3v dc to 15v dc over a wide 5v to 36v input voltage. the typical application schematic is shown in figure 18. the LTM4613 has an integrated constant on-time current mode regulator, ultralow r ds(on) fets with fast switching speed and integrated schottky diodes. the typical switching frequency is 600khz at full load at 12v output. with current mode control and internal feedback loop compensation, the LTM4613 module has sufficient stability margins and good transient performance under a wide range of operat - ing conditions and with a wide range of output capacitors, even all ceramic output capacitors. current mode control provides cycle-by-cycle fast current limiting. moreover, foldback current limiting is provided in an overcurrent condition when v fb drops. internal over - voltage and undervoltage comparators pull the open-drain pgood output low if the output feedback voltage exits a 10% window around the regulation point. furthermore, in an overvoltage condition, internal top fet m1 is turned off and bottom fet m2 is turned on and held on until the overvoltage condition clears. input filter and noise cancellation circuitry reduce the noise coupling to inputs and outputs, and ensure the electromagnetic interference (emi) meets the limits of en55022 class b (see figure 7). pulling the run pin below 1v forces the controller into its shutdown state, turning off both m1 and m2. at light load currents, discontinuous mode (dcm) operation can be enabled to achieve higher efficiency compared to con - tinuous mode (ccm) by setting fcb pin higher than 0.6v. when the drv cc pin is connected to intv cc , an integrated 5v linear regulator powers the internal gate drivers. if a 5v external bias supply is applied on drv cc pin, then an efficiency improvement will occur due to the reduced power loss in the internal linear regulator. this is especially true at the higher input voltage range. the mpgm, marg0, and marg1 pins are used to sup - port voltage margining, where the percentage of margin is programmed by the mpgm pin, while the marg0 and marg1 select positive or negative margining. the pllin pin provides frequency synchronization of the device to an external clock. the track/ss pin is used for power supply tracking and soft-start programming. the typical LTM4613 application circuit is shown in fig - ure?18. external component selection is primarily deter - mined by the input voltage, the maximum load current and the output voltage. refer to table 2 for specific external capacitor requirements for a particular application. v in to v out stepdown ratios there are restrictions in the maximum v in and v out step down ratio that can be achieved for a given input voltage. these constraints are shown in the typical performance characteristic curve labeled v in to v out step-down ratio. note that additional thermal derating may be ap - plied. see the thermal considerations and output current derating section in this data sheet. applications information output voltage programming and margining the pwm controller has an internal 0.6v reference volt - age. as shown in the block diagram, a 100k 0.5% internal feedback resistor connects the v out and v fb pins together. adding a resistor, r fb , from the v fb pin to the sgnd pin programs the output voltage. v out = 0.6v ? 100k + r fb r fb or equivalently, r f b = 100k v out 0.6v ? 1
LTM4613 11 4613f applications information figure 2. operating frequency vs output voltage operating frequency the operating frequency of the LTM4613 is optimized to achieve the compact package size and the minimum output ripple voltage while still keeping high efficiency. as shown in figure 2, the frequency is linearly increased with larger output voltages to keep the low output cur - rent ripple. figure 3 shows the inductor current ripple ?i with different output voltages. in most applications, no additional frequency adjusting is required. if lower output ripple is required, the operating frequency f can be increased by adding a resistor r fset between f set pin and sgnd, as shown in figure 19. f = v out 1.5 ? 10 ? 10 r fset || 133k ( ) figure 3. pk-pk inductor current ripple vs output voltage table 1. r fb standard 1% resistor values vs v out v out (v) 3.3 5 6 8 10 12 14 15 r fb (k) 22.1 13.7 11 8.06 6.34 5.23 4.42 4.12 the mpgm pin programs a current that when multiplied by an internal 10k resistor sets up the 0.6v reference offset for margining. a 1.18v reference divided by the r pgm resistor on the mpgm pin programs the current. calculate v out(margin) : v out(margin) = %v out 100 ? v out where %v out is the percentage of v out to be margined, and v out(margin) is the margin quantity in volts: r pgm = v out 0.6v ? 1.18v v out(margin) ? 10k where r pgm is the resistor value to place on the mpgm pin to ground. the output margining will be margining of the value. this is controlled by the marg0 and marg1 pins. see the truth table below: marg1 marg0 mode low low no margin low high margin up high low margin down high high no margin parallel operation the LTM4613 device is an inherently current mode con - trolled device. this allows the paralleled modules to have very good current sharing and balanced thermal on the design. figure 21 shows a schematic of the parallel design. the voltage feedback equation changes with the variable n as modules are paralleled. the equation: r f b = 100k n v out 0.6v ? 1 where n is the number of paralleled modules. output voltage (v) 2 4 0 frequency (khz) 400 1000 6 10 12 4613 f02 200 800 600 8 14 16 output voltage (v) 2 0 pk-pk inductor current ripple (a) 1 3 4 5 10 9 4613 f03 2 6 4 12 14 8 16 6 7 8 v in = 16v v in = 24v v in = 28v v in = 36v
LTM4613 12 4613f applications information for output voltages more than 12v, the frequency can be higher than 600khz, thus reducing the efficiency signifi- cantly. additionally, the minimum off time 400ns normally limits the operation when the input voltage is close to the output voltage. therefore, it is recommended to lower the frequency in these conditions by connecting a resistor (r fset ) from the f set pin to v in , as shown in figure 20. f = v out 5 ? 10 ? 11 3 ? r fset ? 133k r fset ? 2 ? 133k ? ? ? ? ? ? the load current can affect the frequency due to its con - stant on-time control. if constant frequency is a necessity, the pllin pin can be used to synchronize the frequency of the LTM4613 to an external clock subject to minimum on-time and off-time limits, as shown in figures 21 to 23. input capacitors LTM4613 is designed to achieve the low input conducted emi noise due to the fast switching of turn-on and turn- off. additionally, a high-frequency inductor is integrated into the input line for noise attenuation. v d and v in pins are available for external input capacitors to form a high frequency filter. as shown in figure 18, the ceramic capacitors, c1-c3, on the v d pins is used to handle most of the rms current into the converter, so careful attention is needed for capacitors c1-c3 selection. for a buck converter, the switching duty cycle can be estimated as: d = v out v in without considering the inductor current ripple, the rms current of the input capacitor can be estimated as: i cin(rms) = i out(max) ? d ? 1? d ( ) in this equation, is the estimated efficiency of the power module. note the capacitor ripple current ratings are often based on temperature and hours of life. this makes it advisable to properly derate the input capacitor, or choose a capacitor rated at a higher temperature than required. always contact the capacitor manufacturer for derating requirements. in a typical 8a output application, three very low esr, x5r or x7r, 10f ceramic capacitors are recommended for c1-c3. this decoupling capacitance should be placed directly adjacent to the module v d pins in the pcb layout to minimize the trace inductance and high frequency ac noise. each 10f ceramic is typically good for 2a of rms ripple current. refer to your ceramics capacitor catalog for the rms current ratings. to attenuate the high frequency noise, extra input capacitors should be connected to the v in pads and placed before the high frequency inductor to form the filter. one of these low esr ceramic input capacitors is recommended to be close to the connection into the system board. a large bulk 100f capacitor is only needed if the input source imped - ance is compromised by long inductive leads or traces. output capacitors the LTM4613 is designed for low output voltage ripple. the bulk output capacitors defined as c out are chosen with low enough effective series resistance (esr) to meet the output voltage ripple and transient requirements. c out can be low esr tantalum capacitor, low esr polymer ca - pacitor or ceramic capacitor. the typical capacitance is 4 47f if all ceramic output capacitors are used. additional output filtering may be required by the system designer, if further reduction of output ripple or dynamic transient spike is required. table 2 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 4a load transient. the table optimizes total equivalent esr and total bulk capacitance to maximize transient performance. multiphase operation with multiple LTM4613 devices in parallel will also lower the effective output ripple current due to the phase interleaving operation. refer to figure 4 for the normalized output ripple current versus the duty cycle. figure 4 provides a ratio of peak-to-peak output ripple current to the inductor ripple current as functions of duty cycle and the number of paralleled phases. pick the corresponding duty cycle and the number of phases to get the correct output ripple current value. for example, each phases inductor ripple current ?i l is ~5.0a for a 36v
LTM4613 13 4613f applications information table 2. output voltage response versus component matrix (refer to figure 19) typical measured values vendors part number vendors part number murata grm32er61c476kei5l (47f, 16v) murata grm32er71h106k (10f, 50v) murata grm32er61c226ke20l (22f, 16v) tdk c3225x5ric226m (22f, 16v) figure 4. normalized output ripple current vs duty cycle, ?i l = v o t/l i duty cycle (v o /v in ) 0.1 0.15 0.2 0.25 0.350.3 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 1.00 0.95 0.90 0.85 0.80 0.75 0.70 0.65 0.60 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 4612 f04 6-phase 4-phase 3-phase 2-phase 1-phase peak-to-peak output ripple current ?i l ratio = v out (v) c in (ceramic) c in (bulk) c out1 (ceramic) c out2 (bulk) v in (v) droop (mv) pk-to-pk (mv) recovery time (s) load step (a) load step slew rate (a/s) r fb (k) 3.3 2 10f 50v 100f 50v 2 22uf 16v 150f 16v 5 84 175 50 4 10 22.1 3.3 2 10f 50v 100f 50v 4 47uf 16v none 5 91 181 40 4 10 22.1 3.3 2 10f 50v 100f 50v 2 22uf 16v 150f 16v 12 100 188 50 4 10 22.1 3.3 2 10f 50v 100f 50v 4 47uf 16v none 12 100 191 40 4 10 22.1 3.3 2 10f 50v 100f 50v 2 22uf 16v 150f 16v 24 113 200 50 4 10 22.1 3.3 2 10f 50v 100f 50v 4 47uf 16v none 24 103 197 40 4 10 22.1 5 2 10f 50v 100f 50v 2 22uf 16v 150f 16v 12 109 222 60 4 10 13.7 5 2 10f 50v 100f 50v 4 47uf 16v none 12 122 238 50 4 10 13.7 5 2 10f 50v 100f 50v 2 22uf 16v 150f 16v 24 119 228 60 4 10 13.7 5 2 10f 50v 100f 50v 4 47uf 16v none 24 122 238 50 4 10 13.7 5 2 10f 50v 100f 50v 2 22uf 16v 150f 16v 36 125 231 60 4 10 13.7 5 2 10f 50v 100f 50v 4 47uf 16v none 36 128 247 50 4 10 13.7 12 2 10f 50v 100f 50v 2 22uf 16v 150f 16v 24 178 363 150 4 10 5.23 12 2 10f 50v 100f 50v 4 47uf 16v none 24 238 488 90 4 10 5.23 12 2 10f 50v 100f 50v 2 22uf 16v 150f 16v 36 181 369 150 4 10 5.23 12 2 10f 50v 100f 50v 4 47uf 16v none 36 244 500 90 4 10 5.23
LTM4613 14 4613f applications information to 12v design. the duty cycle is about 0.33. the 2-phase curve shows a ratio of ~0.33 for a duty cycle of 0.33. this 0.33 ratio of output ripple current to the inductor ripple current ?i l at 5.0a equals 1.65a of the output ripple cur - rent (?i o ). the output voltage ripple has two components that are related to the amount of bulk capacitance and effective series resistance (esr) of the output bulk capacitance. the equation is: ? v out(p ? p) ? i o 8 ? f ? n ? c out ? ? ? ? ? ? + esr ? ? i o n where f is the frequency and n is the number of paral - leled phases. fault conditions: current limit and overcurrent foldback LTM4613 has a current mode controller, which inherently limits the cycle-by-cycle inductor current not only in steady state operation, but also in transient. to further limit current in the event of an overload condi - tion, the LTM4613 provides foldback current limiting. if the output voltage falls by more than 50%, then the maximum output current is progressively lowered to about one sixth of its full current limit value. soft-start and tracking the track/ss pin provides a means to either soft-start the regulator or track it to a different power supply. a capacitor on this pin will program the ramp rate of the output voltage. a 1.5a current source will charge up the external soft-start capacitor to 80% of the 0.6v internal voltage reference plus or minus any margin delta. this will control the ramp of the internal reference and the output voltage. the total soft-start time can be calculated as: t softstart ? 0.8 s 0.6 0.6 s v out margin % ( ) c ss 1.5a if the run pin falls below 2.5v, then the soft-start pin is reset to allow for the proper soft-start again. current foldback and force continuous mode are disabled during the soft-start process. the soft-start function can also be used to control the output ramp rising time, so that another regulator can be easily tracked. output voltage tracking output voltage tracking can be programmed externally using the track/ss pin. the output can be tracked up and down with another regulator. figure 5 shows an ex - ample of coincident tracking where the master regulators output is divided down with an external resistor divider that is the same as the slave regulators feedback divider. ratiometric modes of tracking can be achieved by selecting different resistor values to change the output tracking ratio. the master output must be greater than the slave output figure 5. coincident tracking figure 6. coincident output tracking pgood run comp intv cc drv cc track/ss f set v out v fb fcb marg0 marg1 mpgm track control pllin LTM4613 r fb 5.23k 51k master output r2 100k c out slave output 4613 f05 c in v in v d pgnd sgnd v in r1 5.23k 10f 3 output voltage time 4613 f06 master output slave output
LTM4613 15 4613f applications information for the tracking to work. figure 6 shows the coincident output tracking. ratiometric tracking can be achieved by a few simple calculations and the slew rate value applied to the masters track pin. the track pin has a control range from 0 to 0.6v. the masters track pin slew rate is directly equal to the masters output slew rate in volts/time. the equation: mr sr ? 100k = r2 where mr is the masters output slew rate and sr is the slaves output slew rate in volts/time. when coincident tracking is desired, then mr and sr are equal, thus r2 is equal the 100k. r ta is derived from equation: r1 = 0.6v v fb 100k + v fb r fb ? v track r2 where v fb is the feedback voltage reference of the regula - tor, and v track is 0.6v. since r2 is equal to the 100k top feedback resistor of the slave regulator in equal slew rate or coincident tracking, then r1 is equal to r fb with v fb = v track . therefore r2 = 100k, and r1 = 5.23k in figure 5. in ratiometric tracking, a different slew rate maybe desired for the slave regulator. r2 can be solved for when sr is slower than mr. make sure that the slave supply slew rate is chosen to be fast enough so that the slave output voltage will reach it final value before the master output. for example, mr = 1.5v/1ms, and sr = 1.2v/1ms. then r2 = 125k. solve for r1 to equal to 5.18k. each of the track pins will have the 1.5a current source on when a resistive divider is used to implement tracking on that specific channel. this will impose an offset on the track pin input. smaller values resistors with the same ratios as the resistor values calculated from the above equation can be used. for example, where the 100k is used then a 10k can be used to reduce the track pin offset to a negligible value. run enable the run pin is used to enable the power module. the pin has an internal 5.1v zener to ground. the pin can be driven with 5v logic levels. the run pin can also be used as an undervoltage lockout (uvlo) function by connecting a resistor divider from the input supply to the run pin. the equation for uvlo threshold: v uvlo = r a + r b r b ? 1.5v where r a is the top resistor, and r b is the bottom resistor. power good the pgood pin is an open-drain pin that can be used to monitor valid output voltage regulation. this pin monitors a 10% window around the regulation point, and tracks with margining. comp pin the pin is the external compensation pin. the module has already been internally compensated for most output voltages. linear technology provides ltpowercad? for more control loop optimization. fcb pin the fcb pin determines whether the bottom mosfet remains on when current reverses in the inductor. tying this pin above its 0.6v threshold enables discontinuous operation where the bottom mosfet turns off when in - ductor current reverses. fcb pin below the 0.6v threshold forces continuous synchronous operation, allowing current to reverse at light loads and maintaining high frequency operation. pllin pin the power module has a phase-locked loop comprised of an internal voltage controlled oscillator and a phase detector. this allows the internal top mosfet turn-on to be locked to the rising edge of the external clock. the external clock frequency range must be within 30% around the set operating frequency. a pulse detection circuit is used to detect a clock on the pllin pin to turn on the phase- locked loop. the pulse width of the clock has to be at least 400ns. the clock high level must be above 2v and clock
LTM4613 16 4613f applications information low level below 0.3v. during the start-up of the regulator, the phase-locked loop function is disabled. intv cc and drv cc connection an internal low dropout regulator produces an internal 5v supply that powers the control circuitry and drv cc for driving the internal power mosfets. therefore, if the system does not have a 5v power rail, the LTM4613 can be directly powered by v in . the gate driver current through the ldo is about 20ma. the internal ldo power dissipation can be calculated as: p ldo_loss = 20ma ? (v in C 5v) the LTM4613 also provides the external gate driver voltage pin drv cc . if there is a 5v rail in the system, it is recom - mended to connect the drv cc pin to the external 5v rail. this is especially true for higher input voltages. do not apply more than 6v to the drv cc pin. radiated emi noise high radiated emi noise is a disadvantage for switching regulators by nature. fast switching turn-on and turn-off make the large di/dt change in the converters, which act as the radiation sources in most systems. LTM4613 inte - grates the feature to minimize the radiated emi noise to meet the most applications with low noise requirements. an optimized gate driver for the mosfet and a noise cancellation network are installed inside the LTM4613 to achieve the low radiated emi noise. figure 7 shows a typical example for the LTM4613 to meet the en55022 class b radiated emission limit. thermal considerations and output current derating in different applications, LTM4613 operates in a variety of thermal environments. the maximum output current is limited by the environment thermal condition. sufficient cooling should be provided to help ensure reliable opera - tion. when the cooling is limited, proper output current derating is necessary, considering ambient temperature, airflow, input/output condition, and the need for increased reliability. the thermal resistances reported in the pin configura - tion section of the data sheet are consistent with those parameters defined by jesd51-9. they are intended for use with finite element analysis (fea) software modeling tools that leverage the outcome of thermal modeling, simula - tion and correlation to hardware evaluation performed on a module package mounted to a hardware test board. this is also defined by jesd51-9, test boards for area array surface mount package thermal measurements. the motivation for providing these thermal coefficients in found in jesd51-12, guidelines for reporting and using electronic package thermal information. many designers may opt to use laboratory equipment figure 7. radiated emission scan with 24v in to 12v out at 8a measured in 10 meter chamber 70 60 50 40 30 signal amplitude (db uv/m) 20 10 0 30 226.2 422.4 613.6 frequency (mhz) 4613 f07 814.3 1010.0 ?10 en55022b limit
LTM4613 17 4613f and a test vehicle, such as the demo board, to anticipate the module regulators thermal performance in their ap - plication at various electrical and environmental operating conditions to compliment any fea activities. without fea software, the thermal resistances reported in the pin configuration section are in and of themselves not relevant to providing guidance of thermal performance. instead, the derating curves provided in the data sheet can be used in a manner that yields insight and guid - ance pertaining to ones application usage, and can be adapted to correlate thermal performance to ones own application. the pin configuration section of the data sheet typi - cally gives four thermal coefficients, explicitly defined in jesd51 - 12. these coefficients are quoted or paraphrased below: ? ja , the thermal resistance from junction-to-ambient, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclo- sure. this environment is sometimes referred to as still air although natural convection causes the air to move. this value is determined with the part mounted to a jesd51-9 defined test board, which does not reflect an actual application or viable operating condition. ? jcbottom , the thermal resistance from the junction to the bottom of the product case, is the junction-to-board thermal resistance with all of the component power dissipation flowing through the bottom of the pack - age. in the typical module regulator, the bulk of the heat flows out of the bottom of the package, but there is always heat flow out into the ambient environment. as a result, this thermal resistance value may be useful for comparing packages, but the test conditions do not generally match the users application. ? jctop , the thermal resistance from the junction to the top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. as the electrical connections of the module regulator are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. as in the case of jcbottom , this value may be useful for comparing packages, but the test conditions do not generally match the users application. ? jb , the thermal resistance from the junction to the printed circuit board, is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the module regulator and into the board. it is really the sum of the jcbottom and the thermal resistance of the bottom of the part through the solder joints and through a portion of the board. the board temperature is measured a specified distance from the package, using a two-sided, two-layer board. this board is described in jesd51-9. figure 8. graphical representation of jesd51-12 thermal coefficients applications information module regulator 4613 f08 junction a t junction-to-case (top) resistance junction-to-ambient resistance (jesd51-9 defined board) junction-to-board resistance case (top)-to-ambient resistance board-to-ambient resistance case (bottom)-to-board resistance junction-to-case (bottom) resistance
LTM4613 18 4613f a graphical representation of the aforementioned thermal resistances is given in figure 8. blue resistances are contained within the module package, whereas green resistances are external to the module package. as a practical matter, it should be clear to the reader that no individual or sub group of the four thermal resistance parameters defined by jesd51-12, or provided in the pin configuration section, replicates or conveys normal operating conditions of a module regulator . for example, in normal board-mounted applications, never does 100% of the devices total power loss (heat) thermally conduct exclusively through the top or exclusively through bottom of the packageas the standard defines for jctop and jcbottom , respectively. in practice, power loss is thermally dissipated in both directions away from the package. granted, in the absence of a heat sink and airflow, the majority of the heat flow is into the board. within a sip (system-in-package) module, be aware that there are multiple power devices and components dissipat - ing power, with a consequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. to reconcile this complication without sacrificing modeling simplicitybut also, not ignoring practical realitiesan approach has been taken using fea software modeling along with laboratory testing in a controlled environment chamber to reasonably define and correlate the thermal resistance values supplied in this data sheet: 1. initially, fea software is used to accurately build the mechanical geometry of the module regulator and the specified pcb with all of the correct material coefficients, along with accurate power loss source definitions; 2. this model simulates a software-defined jedec envi- ronment consistent with jsed51-9 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the jedec- defined thermal resistance values; applications information 3. the model and fea software is used to evaluate the module regulator with heat sinks and airflow; 4. having solved for, and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled environment chamber while operat - ing the device at the same power loss as that which was simulated. an outcome of this process and due diligence yields a set of derating curves provided in other sections of this data sheet. after these laboratory tests have been performed and correlated to the module regulator model, the jb and ja are summed together to correlate quite well with the module regulator model, with no airflow or heat sink - ing, in a properly defined chamber. this jb + ja value is shown in the pin configuration section, and should accurately equal the ja value in this section, because approximately 100% of power loss flows from the junc - tion through the board into ambient with no airflow or top mounted heat sink. the power loss curves in figures 9 and 10 can be used in coordination with the load current derating curves in figures 11 to 16 for calculating an approximate ja for the module. each figure has three curves that are taken at three different airflow conditions. graph designation delineates between no heat sink, and a bga heat sink. each of the load current derating curves will lower the maxi - mum load current as a function of the increased ambient temperature to keep the maximum junction temperature of the power module at 125c maximum. this will main - tain the maximum operating temperature below 125c. table?3 provides the approximate ja for figures 11 to 16. a complete explanation of the thermal characteristics is provided in the thermal application note, an110.
LTM4613 19 4613f figure 9. power loss at 12v out and 15v out figure 10. power loss at 5v out figure 11. no heat sink with 36v in to 5v out figure 12. bga heat sink with 36v in to 5v out figure 13. no heat sink with 24v in to 12v out figure 14. bga heat sink with 24v in to 12v out applications information figure 15. no heat sink with 36v in to 15v out figure 16. bga heat sink with 36v in to 15v out load current (a) 0 5 6 7 8 4613 f09 4 3 2 4 6 10 2 1 0 power loss (w) 36v in to 15v out 24v in to 12v out load current (a) 0 5 6 7 8 4613 f10 4 3 2 4 6 10 2 1 0 power loss (w) 36v in to 5v out ambient temperature (c) 55 load current (a) 3 4 5 85 105 4613 f11 2 1 0 65 75 95 6 7 8 olfm 200lfm 400lfm ambient temperature (c) 55 load current (a) 3 4 5 85 105 4613 f12 2 1 0 65 75 95 6 7 8 olfm 200lfm 400lfm ambient temperature (c) 55 load current (a) 3 4 5 85 105 4613 f13 2 1 0 65 75 95 6 7 8 olfm 200lfm 400lfm ambient temperature (c) 55 load current (a) 3 4 5 85 105 4613 f14 2 1 0 65 75 95 6 7 8 olfm 200lfm 400lfm ambient temperature (c) 25 35 load current (a) 3 4 5 75 105 4613 f15 2 1 0 45 55 65 85 95 6 7 8 olfm 200lfm 400lfm ambient temperature (c) 25 35 load current (a) 3 4 5 85 105 4613 f16 2 1 0 45 55 65 75 95 6 7 8 olfm 200lfm 400lfm
LTM4613 20 4613f safety considerations the LTM4613 modules do not provide isolation from v in to v out . there is no internal fuse. if required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. layout checklist/example the high integration of LTM4613 makes the pcb board layout very simple and easy. however, to optimize its electrical and thermal performance, some layout consid - erations are still necessary. ? use large pcb copper areas for high current path, in - cluding v in , pgnd and v out . it helps to minimize the pcb conduction loss and thermal stress. ? place high frequency ceramic input and output capaci - tors next to the v d , pgnd and v out pins to minimize high frequency noise. ? place a dedicated power ground layer underneath the unit. ? use round corners for the pcb copper layer to minimize the radiated noise. ? to minimize the emi noise and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers. ? do not put vias directly on pads. ? if vias are placed onto the pads, the the vias must be capped. ? interstitial via placement can also be used if necessary. ? use a separated sgnd ground copper area for com - ponents connected to signal pins. connect the sgnd to pgnd underneath the unit. ? place one or more high frequency ceramic capacitors close to the connection into the system board. figure 17 gives a good example of the recommended layout. applications information table 4. 5v output derating curve v in (v) power loss curve airflow (lfm) heat sink ja (c/w) figure 11 36 figure 10 0 none 11 figure 11 36 figure 10 200 none 9 figure 11 36 figure 10 400 none 9 figure 12 36 figure 10 0 bga heat sink 11 figure 12 36 figure 10 200 bga heat sink 8.5 figure 12 36 figure 10 400 bga heat sink 8.5 heat sink manufacturer wakefield engineering part no: ltn20069 phone: 603-635-2800 table 3. 12v and 15v outputs derating curve v in (v) power loss curve airflow (lfm) heat sink ja (c/w) figures 13, 15 24, 36 figure 9 0 none 14 figures 13, 15 24, 36 figure 9 200 none 10 figures 13, 15 24, 36 figure 9 400 none 10 figures 14, 16 24, 36 figure 9 0 bga heat sink 13 figures 14, 16 24, 36 figure 9 200 bga heat sink 8 figures 14, 16 24, 36 figure 9 400 bga heat sink 8
LTM4613 21 4613f applications information figure 18. typical 22v to 36v in , 12v at 8a design pgood run comp intv cc drv cc f set track/ss fcb marg0 marg1 mpgm v out v fb pull-up supply 5v r3 51k c4 0.1f c5 22pf c out1 22f 16v c out2 180f 16v c in 10f 50v ceramic v in 22v to 36v clock sync refer to table 2 on/off LTM4613 sgnd pgnd margin control r4 51k r fb 5.23k r1 392k 5% margin + 4613 f18 v d v in pllin c1 to c3 10f 50v 3 v out 12v 8a figure 17. recommended pcb layout v in v out gnd c in c vd c vd c out c out 4613 f17
LTM4613 22 4613f figure 20. 26v to 36v in , 15v at 5a design with 600khz frequency pgood run comp intv cc drv cc f set track/ss fcb marg0 marg1 mpgm v out v fb pull-up supply 5v r3 51k c4 0.1f c5 22pf c out1 22f 16v c out2 220f 16v c in 10f 50v ceramic v in 26v to 36v clock sync refer to table 2 on/off LTM4613 sgnd pgnd margin control r4 51k r fb 4.12k r fset 562k 1% r1 392k 5% margin + 4613 f20 v d v in pllin v out 15v 5a c1 to c3 10f 50v 3 applications information figure 19. typical 5v to 36v in , 3.3v at 8a design with 400khz frequency pgood run comp intv cc drv cc f set track/ss fcb marg0 marg1 mpgm v out v fb pull-up supply 5v r3 51k c4 0.1f c5 22pf c out1 22f 6.3v c out2 180f 6.3v c in 10f 50v ceramic v in 5v to 36v clock sync refer to table 2 external 5v supply improves efficiency? especially for high input voltages on/off LTM4613 sgnd pgnd margin control r4 51k r fset 93.1k 1% r fb 22.1k r1 392k 5% margin + 4613 f19 v d v in pllin v out 3.3v 8a c1 to c3 10f 50v 3
LTM4613 23 4613f pgood run comp intv cc drv cc f set track/ss v out v fb fcb marg0 marg1 mpgm pull-up supply 5v r2 51k c7 0.33f c6 47pf c3 22f 16v 4613 f21 c4 180f 16v c11 0.1f c5 100f 50v c2 10f 50v c8 10f 50v v in 20v to 36v ltc6908-1 2-phase oscillator clock sync 0 phase clock sync 180 phase LTM4613 sgnd pgnd pgood run comp intv cc drv cc f set track/ss LTM4613 sgnd pgnd margin control 5% margin r4 51k r fb 2.61k r1 392k r5 166k v + gnd set out1 out2 mod + v out v fb fcb marg0 marg1 mpgm c9 22f 16v c10 180f 16v r6 392k + + v out = 0.6v ? 100k/n + r fb r fb v d v in pllin v d v in pllin v out 12v 16a c1 10f 50v 3 c11 10f 50v 3 figure 21. 2-phase, parallel 12v at 16a design with 600khz frequency applications information
LTM4613 24 4613f pgood run comp intv cc drv cc f set track/ss v out v fb fcb marg0 marg1 mpgm pull-up supply 5v r2 51k c7 0.1f c6 22pf c3 22f 16v 4613 f22 c4 180f 16v 12v 6a c11 0.1f c5 100f 50v c2 10f 50v c8 10f 50v v in 22v to 36v ltc6908-1 2-phase oscillator clock sync 0 phase clock sync 180 phase LTM4613 sgnd pgnd pgood run comp intv cc drv cc f set track/ss LTM4613 sgnd 12v track pgnd margin control 5% margin r4 51k r fb1 5.23k r fb2 6.34k r1 392k r8 100k r9 6.34k r3 51k r7 51k pull-up supply 5v r5 166k v + gnd set out1 out2 mod + v out v fb fcb marg0 marg1 mpgm c1 22pf c9 22f 16v c10 180f 16v 10v 6a margin control r6 392k + + v d v in pllin v d v in pllin c11 10f 50v 3 c1 10f 50v 3 figure 22. 2-phase, 12v and 10v at 6a design with 600khz frequency and output voltage tracking applications information
LTM4613 25 4613f drv cc f set track/ss pgood run comp intv cc fcb marg0 marg1 mpgm v out v fb v d v in 5v r2 51k c7 0.15f c6 22pf c3 22f 6.3v 4613 f23 c4 180f 6.3v 5v 8a c11 0.1f c5 100f 50v c2 10f 50v c8 10f 50v v in 7v to 36v ltc6908-1 2-phase oscillator pllin clock sync 0 phase clock sync 180 phase sgnd pgnd pgood run comp intv cc drv cc f set track/ss v in v d pllin sgnd 5v track pgnd margin control r4 51k r fset1 133k r fb1 13.7k r1 392k r8 100k r9 22.1k r fset2 64.9k r3 51k r7 51k 3.3v r5 200k v + gnd set out1 out2 mod + v out v fb fcb marg0 marg1 mpgm c1 22pf c9 22f 6.3v c10 180f 6.3v 3.3v 8a margin control r fb2 22.1k r6 392k + + LTM4613 LTM4613 5% margin c1 10f 50v 3 c11 10f 50v 3 figure 23. 2-phase, 5v and 3.3v at 8a design with 500khz frequency and output voltage tracking applications information
LTM4613 26 4613f pin name a1 a2 a3 a4 a5 v in v in v in v in v in b1 b2 b3 b4 b5 v in v in v in v in v in pin assignment tables (arranged by pin function) pin name d1 d2 d3 d4 d5 d6 pgnd pgnd pgnd pgnd pgnd pgnd e1 e2 e3 e4 e5 e6 e7 e8 pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd f1 f2 f3 f4 f5 f6 f7 f8 f9 pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd g1 g2 g3 g4 g5 g6 g7 g8 g9 g10 g11 pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pin name j1 j2 j3 j4 j5 j6 j7 j8 j9 j10 j11 v out v out v out v out v out v out v out v out v out v out v out k1 k2 k3 k4 k5 k6 k7 k8 k9 k10 k11 v out v out v out v out v out v out v out v out v out v out v out l1 l2 l3 l4 l5 l6 l7 l8 l9 l10 l11 v out v out v out v out v out v out v out v out v out v out v out m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 v out v out v out v out v out v out v out v out v out v out v out pin name a6 a7 a8 a9 a10 a11 a12 v d intv cc pllin track/ss run comp mpgm b6 b7 b8 b9 b10 b11 b12 v d v d C run C mpgm f set c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 v d v d v d v d v d v d v d C C drv cc marg1 marg0 d7 d8 d9 d10 d11 d12 C C sgnd C comp marg1 e9 e10 e11 e12 C C drv cc drv cc f10 f11 f12 C C v fb g12 pgood h12 sgnd j12 nc k12 nc l12 nc m12 fcb package description
LTM4613 27 4613f package description information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. detail b detail b substrate mold cap // bbb z z a notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters land designation per jesd mo-222, spp-010 5. primary datum -z- is seating plane 6. the total number of pads: 133 4 3 details of pad #1 identifier are optional, but must be located within the zone indicated. the pad #1 identifier may be either a mold or marked feature package top view 4 pad ?a1? corner x y aaa z aaa z package bottom view 3 see notes suggested pcb layout top view detail a f g h l m j k e a b c d 2 1 4 3 12 11 9 5 10 678 d 0.630 0.025 ? 133x e b e e b f g lga 133 0610 rev ? tray pin 1 bevel package in tray loading orientation component pin ?a1? symbol a b d e e f g h1 h2 aaa bbb eee min 4.22 0.60 0.27 3.95 nom 4.32 0.63 15.0 15.0 1.27 13.97 13.97 0.32 4.00 max 4.42 0.66 0.37 4.05 0.15 0.10 0.05 notes dimensions total number of lga pads: 133 ltmxxxxxx module h2 h1 detail a 0.630 0.025 sq. 133x s yxeee c(0.30) pad 1 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 0.0000 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 0.0000 lga package 133-lead (15mm 15mm 4.32mm) (reference ltc dwg # 05-08-1884 rev ?)
LTM4613 28 4613f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2011 lt 0411 ? printed in usa related parts package photograph part number description comments ltm4606 en55022b compliant 28v in , 6a dc/dc module regulator en55022 class b certified with pll, output tracking and margining, ltm4600 10a dc/dc module regulator basic 10a dc/dc module regulator, lga package ltm4600hvmp military plastic 10a dc/dc module regulator guaranteed operation from C55c to 125c ambient, lga package ltm4601/ ltm4601a 12a dc/dc module regulator with pll, output tracking/ margining and remote sensing synchronizable, polyphase operation, ltm4601-1/ltm4601a-1 version has no remote sensing, lga package ltm4602 6a dc/dc module regulator pin compatible with the ltm4600, lga package ltm4603 6a dc/dc module regulator with pll and output tracking/margining and remote sensing synchronizable, polyphase operation, ltm4603-1 version has no remote sensing, pin compatible with the ltm4601, lga package ltm4604a low v in 4a dc/dc module regulator 2.375v v in 5.5v, 0.8v v out 5v, 9mm 15mm 2.3mm lga package ltm4608a low v in 8a dc/dc module regulator 2.7v v in 5.5v; 0.6v v out 5v; 9mm 15mm 2.8mm lga package ltm8020 high v in 0.2a dc/dc step-down module regulator 4v v in 36v, 1.25v v out 5v 6.25mm 6.25mm 2.3mm lga package ltm8021 high v in 0.5a dc/dc step-down module regulator 3v v in 36v, 0.8v v out 5v 6.25mm 11.25mm 2.8mm lga package ltm8022/ ltm8023 36v in , 1a and 2a dc/dc module regulator pin compatible; 3.6v v in 36v; 9mm 11.25mm 2.8mm lga package ltm4612 en55022b compliant 36v in , 5a module regulator pll input, 5v v in 36v, 15mm 15mm 2.8mm lga package

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